Operand History Table

Operand pre-fetching for faster instruction executions is described. Trace analysis has shown that many of the instructions that require an operand compute the same operand address each time that the instruction is executed. Consider the instruction format below: (Image Omitted) The operand address is computed by adding the contents of the base register to the contents of the index register to the value of the displacement field supplied by the instruction. That is, operand address = C(B) + C(X) + displacement. This calculation is normally performed at address generation (AGEN) time. The operands are then fetched from the cache or memory. The time needed to fetch the operands depends on the speed of the cache or memory. Fig. 1 ...

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Operand History Table

Operand pre-fetching for faster instruction executions is described. Trace analysis has shown that many of the instructions that require an operand compute the same operand address each time that the instruction is executed. Consider the instruction format below:

(Image Omitted)

The operand address is computed by adding the contents of the base register to the contents of the index register to the value of the displacement field supplied by the instruction. That is, operand address = C(B) + C(X) + displacement. This calculation is normally performed at address generation (AGEN) time. The operands are then fetched from the cache or memory. The time needed to fetch the operands depends on the speed of the cache or memory. Fig. 1 represents an idealized, cycle by cycle description of an instruction passing through a pipeline. The decode, AGEN, operand fetch (C1,C2), and execution phases are represented. Fig. 2 shows a mechanism that can fetch operands for instructions with constant operand addresses before the instructions are even decoded. The operand history table (O.H.T.) holds the instruction address and operand address of each instruction that computes the same operand address each time it is executed. Each entry in the O.H.T. contains two addresses. The first is the instruction address. The second entry is the address of the operand for that instruction. The mechanism shown in Fig. 2 operates as follows: Each instruction address fetched b...